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LTC6412 1 6412f typical application description 800mhz, 31db range analog-controlled vga the ltc ? 6412 is a fully differential variable gain ampli? er with linear-in-db analog gain control. it is designed for ac-coupled operation in if receiver chains from 1mhz to 500mhz. the part has a constant oip3 across a wide output amplitude range and across the 31db gain control range. the output noise (nf + gain) is also ? at versus gain to provide a uniform spurious-free dynamic range (sfdr) >120db over the full gain control range at 240mhz. the LTC6412 is ideal for interfacing with the lt ? 5527 and lt5557 downconverting mixers, ltc6410-6 if ampli? er and the ltc6400/ltc6401/ltc6416 adc drivers for use in 12-, 14-, and 16-bit adc applications. the LTC6412 recovers quickly from an overdrive condition, and the en pin allows for a fast output signal disable to protect sensitive downstream components. asserting the shdn pin reduces the current consumption below 1ma for power-down or sleep modes. 3.3v fully differential 240mhz if receiver chain with 31db gain control features applications n 800mhz C3db small-signal bandwidth n continuously-adjustable gain control n C14db to +17db linear-in-db gain range n 35dbm oip3 at 240mhz across all gain settings n 10db noise figure at maximum gain n (iip3 C nf) = +8dbm at 240mhz across all gains n 2.7nv/ hz input referred noise n differential inputs and outputs n 50 input impedance across all gains n single supply operation from 3v to 3.6v n 110ma supply current n 4mm 4mm 0.75mm 24-pin qfn package n if signal chain automatic gain control (agc) n 2.5g and 3g cellular basestation transceivers n wimax, wibro, wlan receivers n satellite and gps receiver if v cc shdn en gnd v cm v ref decl1 decl2 Cv g +v g +in 10nf 0.1f bpf v cm gnd 6412 ta01 v dd ltc2208 0.1f 3.3v 1nf 0.1f 180nh 180nh 3.3v 3.3v 3.3v +out Cout a in + a in C Cout +out 10nf 10nf 0.1f 0.1f 0.1f gain control (+ slope mode) if input +in v + v C v cm ltc6400-8 Cin LTC6412 Cin 2.2f vga gain vs frequency over gain control range frequency (mhz) C20 gain (db) C10 0 10 20 1 100 1000 10000 6412 g01 C30 10 g max g min l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
LTC6412 2 6412f total supply voltage (v cc to gnd) ...........................3.8v ampli? er input current (+in, Cin) ........................20ma ampli? er output current (+out, Cout) ...............70ma input current (+v g , Cv g , v ref , en , shdn ) .........10ma input current (v cm , decl1, decl2) ....................10ma rf input power, continuous, 50 ......................+15dbm rf input power, 100s pulse, 50 ....................+20dbm operating temperature range (note 2).... C40c to 85c speci? ed temperature range (note 3) .... C40c to 85c storage temperature range ................... C65c to 150c junction temperature ........................................... 150c (note 1) 24 23 22 21 20 19 7 8 9 top view uf package 24-lead (4mm s 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 gnd +in Cin v cm v cm v cc gnd +out Cout gnd decl2 v cc v cc gnd shdn en gnd v cc decl1 gnd +v g v ref Cv g gnd 25 t jmax = 150c, ja = 37c/w exposed pad (pin 25) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description specified temperature range LTC6412cuf#pbf LTC6412cuf#trpbf 6412 24-lead (4mm 4mm) plastic qfn 0c to 70c LTC6412iuf#pbf LTC6412iuf#trpbf 6412 24-lead (4mm 4mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ pin configuration absolute maximum ratings
LTC6412 3 6412f dc electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. dc electrical performance measured using dc test circuit schematic. v in(diff) is de? ned as (+in) C (Cin). v out(diff) is de? ned as (+out) C (Cout). v in(cm) is de? ned as [(+in) + (Cin)]/2. v out(cm) is de? ned as [(+out) + (Cout)]/2. unless noted otherwise, default operating conditions are v cc = 3.3v, en = 0.8v, shdn = 2.2v, +v g tied to v ref (negative gain slope mode), v out(cm) = 3.3v. differential power gain de? ned at z source = 50 differential and z load = 200 differential. symbol parameter conditions min typ max units gain characteristics g max maximum differential power gain (note 4) Cv g = 0v, v in(diff) = 100mv l 16.1 15.5 17.1 18.1 18.7 db db g min minimum differential power gain (note 4) Cv g = 1.2v, v in(diff) = 200mv l C16.2 C16.8 C14.9 C13.6 C13.0 db db g range differential power gain range g max -g min l 30.7 30.1 31.9 33.1 33.7 db db tc gain temperature coef? cient of gain at fixed v g Cv g = 0v to 1.2v 0.007 db/c g slope gain control slope Cv g = 0.2v to 1.0v, 85 points, slope of the least-square fit line l C34.1 C34.7 C32.9 C31.7 C31.1 db/v db/v g conf(ave) average conformance error to gain slope line Cv g = 0.2v to 1.0v, 85 points, standard error to the least-square fit line 0.12 0.20 db g conf(max) maximum conformance error to gain slope line Cv g = 0.2v to 1.0v, 85 points, maximum error to the least-square fit line 0.20 0.45 db +in and Cin pins r in(gmax) differential input resistance at maximum gain Cv g = 0v, v in(diff) = 100mv l 49 47 57 65 67 r in(gmin) differential input resistance at minimum gain Cv g = 1.2v, v in(diff) = 200mv l 49 47 57 65 67 v incm(gmax) input common mode voltage at maximum gain Cv g = 0v, dc blocking capacitor to input 640 mv v incm(gmin) input common mode voltage at minimum gain Cv g = 1.2v, dc blocking capacitor to input 640 mv +v g , Cv g , and v ref pins r ih(+vg) +v g input high resistance +v g = 1.0v, Cv g tied to v ref , r in(+vg) = 1v/ i il(+vg) l 7.8 7.2 9.2 10.6 11.6 k k r ih(Cvg) Cv g input high resistance Cv g = 1.0v, +v g tied to v ref , r in(Cvg) = 1v/ i il(Cvg) l 7.8 7.2 9.2 10.6 11.6 k k i il(+vg) +v g input low current +v g = 0v, Cv g tied to v ref l C9 C10 C5 C1 C1 a a i il(Cvg) Cv g input low current Cv g = 0v, +v g tied to v ref l C9 C10 C5 C1 C1 a a v ref internal bias voltage Cv g = 0v, +v g tied to v ref l 590 580 615 640 650 mv mv
LTC6412 4 6412f dc electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. dc electrical performance measured using dc test circuit schematic. v in(diff) is de? ned as (+in) C (Cin). v out(diff) is de? ned as (+out) C (Cout). v in(cm) is de? ned as [(+in) + (Cin)]/2. v out(cm) is de? ned as [(+out) + (Cout)]/2. unless noted otherwise, default operating conditions are v cc = 3.3v, en = 0.8v, shdn = 2.2v, +v g tied to v ref (negative gain slope mode), v out(cm) = 3.3v. differential power gain de? ned at z source = 50 differential and z load = 200 differential. symbol parameter conditions min typ max units shdn pin v il( shdn ) shdn input low voltage l 0.8 v v ih( shdn ) shdn input high voltage l 2.2 v i il( shdn ) shdn input low current shdn = 0.8v l C60 C30 C1 a i ih( shdn ) shdn input high current shdn = 2.2v l C30 C15 C1 a en pin v il( en ) en input low voltage l 0.8 v v ih( en ) en input high voltage l 2.2 v i il( en ) en input low current en = 0.8v l C60 C30 C1 a i ih( en ) en input high current en = 2.2v l C30 C15 C1 a power supply v s operating supply range l 3.0 3.3 3.6 v i s(tot) total supply current all v cc pins plus +out and Cout pins l 110 135 140 ma ma i s(out) sum of supply current to out pins i s(out) = i +out + i Cout l 44 55 60 ma ma i (out) delta of supply current to out pins current imbalance to +out and Cout l 0.5 1.5 2.0 ma ma i s( shdn ) supply current in shutdown i s(out) at shdn = 0.8v l 0.5 1.3 2.0 ma ma psrr max power supply rejection ratio at max gain Cv g = 0v, output referred 40 53 db psrr min power supply rejection ratio at min gain Cv g = 1.2v, output referred 40 53 db
LTC6412 5 6412f ac electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. typical ac electrical performance measured in demo board dc1464a (figure 3, test circuit a) unless otherwise noted. default operating conditions are v cc = 3.3v, en = 0.8v, shdn = 2.2v, +v g tied to v ref (negative gain slope mode), and z source = z load = 50 unless otherwise noted. symbol parameter conditions min typ max units small signal bw gmax C3db bandwidth for sdd21 at maximum gain Cv g = 0v, test circuit b 800 mhz bw gmin C3db bandwidth for sdd21 at minimum gain Cv g = 1.2v, test circuit b 800 mhz sdd11 input match at z source = 50 differential Cv g = 0v to 1.2v, 10mhz-500mhz, test circuit b C20 db sdd22 output match at z load = 200 differential Cv g = 0v to 1.2v, 10mhz-250mhz, test circuit b C10 db sdd12 reverse isolation Cv g = 0v to 1.2v, 10mhz-500mhz, test circuit b -80 db transient response t step(6db) 6db gain step response time peak p out = +4dbm, Cv g = 0.2v to 0.4v, time to settle within 1db of final p out 0.4 s t step(12db) 12db gain step response time peak p out = +4dbm, Cv g = 0.2v to 0.6v, time to settle within 1db of final p out 0.4 s t step(20db) 20db gain step response time peak p out = +4dbm, Cv g = 0.2v to 0.8v, time to settle within 1db of final p out 0.4 s t ovdr overdrive recovery time at 70mhz Cv g = 0v, p in = +3dbm to C17dbm, time to settle within 1db of final p out 25 ns t off output ampli? er disable time p out = 0dbm at en = 0v, Cv g = 0v, en = 0v to 3v, time for p out C20dbm 25 ns t on output ampli? er enable time p out = 0dbm at en = 0v, Cv g = 0v, en = 3v to 0v, time for p out C1dbm 20 ns 70mhz signal g max maximum gain Cv g = 0v, test circuit b 17 db g min minimum gain Cv g = 1.2v, test circuit b C15 db g range gain range g max -g min 32 db hd2 second harmonic distortion p out = 0dbm, Cv g = 0v to 1.0v C80 dbc hd3 third harmonic distortion p out = 0dbm, Cv g = 0v to 1.0v C80 dbc im3 third-order intermodulation f 1 = 69.5mhz, f 2 = 70.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v C90 dbc oip3 output third-order intercept f 1 = 69.5mhz, f 2 = 70.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v 39 dbm p1db gmax output 1db compression point at max gain Cv g = 0v (note 6) 13 dbm nf gmax noise figure at maximum gain Cv g = 0v (note 5) 10 db nf gmin noise figure at minimum gain Cv g = 1.2v (note 5) 42 db 140mhz signal g max maximum gain Cv g = 0v, test circuit b 17 db g min minimum gain Cv g = 1.2v, test circuit b C15 db g range gain range g max -g min 32 db hd2 second harmonic distortion p out = 0dbm, Cv g = 0v to 1.0v C80 dbc hd3 third harmonic distortion p out = 0dbm, Cv g = 0v to 1.0v C75 dbc
LTC6412 6 6412f ac electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. typical ac electrical performance measured in demo board dc1464a (figure 3, test circuit a) unless otherwise noted. default operating conditions are v cc = 3.3v, en = 0.8v, shdn = 2.2v, +v g tied to v ref (negative gain slope mode), and z source = z load = 50 unless otherwise noted. symbol parameter conditions min typ max units im3 third-order intermodulation f 1 = 139.5mhz, f 2 = 140.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v C88 dbc oip3 output third-order intercept f 1 = 139.5mhz, f 2 = 140.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v 38 dbm p1db gmax output 1db compression point at max gain Cv g = 0v (note 6) 13 dbm nf gmax noise figure at maximum gain Cv g = 0v (note 5) 10 db nf gmin noise figure at minimum gain Cv g = 1.2v (note 5) 42 db 240mhz signal g max maximum gain Cv g = 0v, test circuit b 17 db g min minimum gain Cv g = 1.2v, test circuit b C14 db g range gain range g max -g min 31 db hd2 second harmonic distortion p out = 0dbm, Cv g = 0v to 1.0v C70 dbc hd3 third harmonic distortion p out = 0dbm, Cv g = 0v to 1.0v C70 dbc im3 third-order intermodulation f 1 = 239.5mhz, f 2 = 240.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v C82 dbc oip3 output third-order intercept f 1 = 239.5mhz, f 2 = 240.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v 35 dbm p1db gmax output 1db compression point at max gain Cv g = 0v (note 6) 12 dbm nf gmax noise figure at maximum gain Cv g = 0v (note 5) 10 db nf gmin noise figure at minimum gain Cv g = 1.2v (note 5) 42 db 280mhz/320mhz signal g max maximum gain f = 320mhz, p out = C3dbm, Cv g = 0v 16.9 db g mid medium gain f = 320mhz, p out = C5dbm, Cv g = 0.6v 1.5 db g min minimum gain f = 320mhz, p out = C5dbm, Cv g = 1.2v C14.2 db g range gain range 320mhz, g max -g min 29.7 31.1 32.5 db im3 gmax third-order intermodulation at max gain f 1 = 280mhz, f 2 = 320mhz, p out = C3dbm/tone, Cv g = 0v C72 dbc im3 gmid third-order intermodulation at mid gain f 1 = 280mhz, f 2 = 320mhz, p out = C5dbm/tone, Cv g = 0.6v C71 C65 dbc im3 gmin third-order intermodulation at min gain f 1 = 280mhz, f 2 = 320mhz, p out = C5dbm/tone, Cv g = 1.2v C56 dbc oip3 gmax output third-order intercept at max gain f 1 = 280mhz, f 2 = 320mhz, p out = C3dbm/tone, Cv g = 0v 31.0 dbm oip3 gmid output third-order intercept at mid gain f 1 = 280mhz, f 2 = 320mhz, p out = C5dbm/tone, Cv g = 0.6v 26.0 30.5 dbm oip3 gmin output third-order intercept at min gain f 1 = 280mhz, f 2 = 320mhz, p out = C5dbm/tone, Cv g = 1.2v 23.0 dbm
LTC6412 7 6412f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. rf input power rating is guaranteed by design and engineering characterization, but not production tested. the absolute maximum continuous rf input power shall not exceed +15dbm note 2: the LTC6412c/LTC6412i are guaranteed functional over the operating temperature range of C40c to 85c. note 3: the LTC6412c is guaranteed to meet speci? ed performance from 0c to 70c. it is designed, characterized and expected to meet speci? ed performance from C40c and 85c but is not tested or qa sampled at these temperatures. the lt6412i is guaranteed to meet speci? ed performance from C40c to 85c. note 4: power gain is de? ned at z source = 50 and z load = 200. voltage gain for this test condition is 6db higher than the stated power gain. note 5: e n can be calculated from 50 nf with the formula: e n = {4kt(50)(10 nf/10 C 1)} where e n = input referred voltage noise in v/ hz nf = 50 noise ? gure in db k = boltzmanns constant = 1.38 ? 10 C23 j/k t = absolute temperature in k = c + 273 note 6: p1db compression of the output ampli? er cannot be achieved in the minimum gain state while complying with the absolute maximum rating for input rf power. ac electrical characteristics the l denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. typical ac electrical performance measured in demo board dc1464a (figure 3, test circuit a) unless otherwise noted. default operating conditions are v cc = 3.3v, en = 0.8v, shdn = 2.2v, +v g tied to v ref (negative gain slope mode), and z source = z load = 50 unless otherwise noted. symbol parameter conditions min typ max units 380mhz signal g max maximum gain Cv g = 0v, test circuit b 17 db g min minimum gain Cv g = 1.2v, test circuit b C14 db g range gain range g max -g min 31 db im3 third-order intermodulation f 1 = 379.5mhz, f 2 = 380.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v C72 dbc oip3 output third-order intercept f 1 = 379.5mhz, f 2 = 380.5mhz, p out = C6dbm/tone, Cv g = 0v to 1.0v 30 dbm p1db gmax output 1db compression point at max gain Cv g = 0v (note 6) 11 dbm nf gmax noise figure at maximum gain Cv g = 0v (note 5) 10.5 db nf gmin noise figure at minimum gain Cv g = 1.2v (note 5) 42 db
LTC6412 8 6412f typical performance characteristics differential input match (sdd11) vs frequency over 11 gain settings differential reverse isolation (sdd12) vs frequency over 6 gain settings differential output smith chart (sdd22) 10mhz to 500mhz over 6 gain settings supply current vs supply voltage over temperature differential gain (sdd21) vs frequency over 11 gain settings common mode gain (scc21) vs frequency over 11 gain settings cm-to-dm gain (sdc21) vs frequency over 11 gain settings electrical performance in test circuits a and b at t a = 25c and v cc = 3.3v unless otherwise noted. differential output match (sdd22) vs frequency over 11 gain settings differential input smith chart (sdd11) 10mhz to 500mhz over 6 gain settings frequency (mhz) C20 gain (db) C10 0 10 20 1 100 1000 10000 6412 g01 C30 10 g max g min frequency (mhz) C60 gain (db) C40 C20 0 20 1 100 1000 10000 6412 g02 C80 10 g max g min frequency (mhz) C60 gain (db) C40 C20 0 1 100 1000 10000 6412 g03 C80 10 g max g min frequency (mhz) C30 return loss (db) C20 C10 0 1 100 1000 10000 6412 g04 C40 10 g max g min frequency (mhz) C30 return loss (db) C20 C10 0 1 100 1000 10000 6412 g05 C40 10 g max g min frequency (mhz) C100 isolation (db) C80 C60 C40 1 100 1000 10000 6412 g06 C120 10 g max g min g min 6412 g07 z o = 50 g max 10mhz z o = 200 120mhz g max g min 240mhz 380mhz 500mhz 6412 g08 supply voltage (v) 3.0 90 total supply current (ma) 95 100 105 110 120 3.1 3.2 3.3 3.4 6412 g09 3.5 3.6 115 85c C40c 30c 0c
LTC6412 9 6412f output ip3 vs control voltage over tone spacing output ip3 vs control voltage over output power per tone 3rd harmonic distortion vs control voltage over v cc differential gain (sdd21) vs control voltage over temperature gain (sdd21) conformance error vs control voltage over temperature relative phase (sdd21) vs control voltage over frequency typical performance characteristics electrical performance in test circuits a and b at t a = 25c and v cc = 3.3v unless otherwise noted. output ip3 at 140mhz vs control voltage over temperature output ip3 vs control voltage over frequency output ip3 at 140mhz vs control voltage over v cc +v g or Cv g voltage (v) 0 gain (db) C5 0 5 0.6 1.0 6412 g10 C10 C15 C20 0.2 0.4 0.8 10 15 20 1.2 C40c 25c 85c Cv g : negative slope mode +v g : positive slope mode freq = 140mhz Cv g voltage (v) 0 C5 gain conformance error (db) C3 C1 1 0.2 g max g min 0.4 0.6 0.8 6412 g11 1.0 3 5 C4 C2 0 2 4 1.2 freq = 140mhz C40c 85c 25c Cv g voltage (v) 0 sdd21 phase relative to g max (deg) C5 0 5 0.6 1.0 g min g max 6412 g12 C10 C15 C20 0.2 0.4 0.8 10 15 20 1.2 400mhz phase adv. phase delay 100mhz 200mhz Cv g voltage (v) 0 45 40 35 30 25 20 15 10 0.6 1.0 6412 g13 0.2 g max g min 0.4 0.8 1.2 oip3 (dbm) C40c 25c 85c p out = C6dbm/tone freq = 1mhz Cv g voltage (v) 0 45 70mhz 40 35 30 25 20 15 10 0.6 1.0 6412 g14 0.2 g max g min 0.4 0.8 1.2 oip3 (dbm) p out = C6dbm/tone freq = 1mhz 140mhz 240mhz 380mhz Cv g voltage (v) 0 45 40 35 30 25 20 15 10 0.6 1.0 6412 g15 0.2 g max g min 0.4 0.8 1.2 oip3 (dbm) 3.6v 3.3v 3v p out = C6dbm/tone freq = 1mhz Cv g voltage (v) 0 45 40 35 30 25 20 15 10 0.6 1.0 6412 g16 0.2 g max g min 0.4 0.8 1.2 oip3 (dbm) p out = C6dbm/tone freq = 140mhz spacing = 0.5mhz 1mhz 2mhz 5mhz Cv g voltage (v) 0 45 40 35 30 25 20 15 10 0.6 1.0 6412 g17 0.2 g max g min 0.4 0.8 1.2 oip3 (dbm) freq = 140mhz freq = 1mhz p out = C6dbm/tone C3dbm/tone C9dbm/tone test equipment limited input attenuator limited Cv g voltage (v) 0 C120 hd3 (dbc) C100 C80 C60 C40 C20 0.2 g max g min 0.4 0.6 0.8 6412 g18 1.0 1.2 freq = 140mhz p out = 0dbm v cc = 3v v cc = 3.6v v cc = 3.3v
LTC6412 10 6412f typical performance characteristics 2nd harmonic distortion vs control voltage over p out 140mhz noise figure vs gain setting over temperature output p 1db at g max vs frequency over supply voltage input and output p 1db vs gain setting at 140mhz 140mhz sideband noise near g max at p out = +8dbm 2nd harmonic vs distortion vs control voltage over frequency 3rd harmonic distortion vs control voltage over frequency noise figure at g max vs frequency over temperature electrical performance in test circuits a and b at t a = 25c and v cc = 3.3v unless otherwise noted. 3rd harmonic distortion vs control voltage over p out Cv g voltage (v) 0 C120 hd2 (dbc) C100 C80 C60 C40 C20 0.2 g max g min 0.4 0.6 0.8 6412 g19 1.0 1.2 p out = 0dbm freq = 280mhz freq = 140mhz freq = 70mhz Cv g voltage (v) 0 C120 hd3 (dbc) C100 C80 C60 C40 C20 0.2 g max g min 0.4 0.6 0.8 6412 g20 1.0 1.2 p out = 0dbm freq = 280mhz freq = 70mhz freq = 140mhz frequency (mhz) 0 noise figure (db) 8 10 12 300 6412 g21 6 4 100 200 400 250 50 150 350 2 0 14 85c C40c 25c Cv g voltage (v) 0 C120 hd2 (dbc) C100 C80 C60 C40 C20 0.2 g max g min 0.4 0.6 0.8 6412 g22 1.0 1.2 freq = 140mhz p out = 3dbm p out = 0dbm p out = C3dbm input attenuator limited Cv g voltage (v) 0 C120 hd3 (dbc) C100 C80 C60 C40 C20 0.2 g max g min 0.4 0.6 0.8 6412 g23 1.0 1.2 freq = 140mhz input attenuator limited p out = 3dbm p out = C3dbm p out = 0dbm gain setting (db) C20 noise figure (db) 25 30 35 20 6412 g24 20 15 0 C10 0 10 C15 C5 5 15 10 5 45 85c 40 C40c 25c frequency (mhz) 0 0 output p1db (dbm) 2 6 8 10 20 3.6v 3.3v 14 100 200 250 6412 g25 4 16 18 12 50 150 300 350 400 3v gain setting (db) C20 p1db (dbm) 10 15 20 C5 5 20 6412 g26 5 0 C5 C15 C10 0 10 15 input p1db output p1db input attenuator limited output amplifier limited offset from 140mhz (hz) C20000 20000 power density (dbc/hz) C60 C40 C20 6412 g27 C80 C100 C10000 10000 0 C120 C140 0 gain = g max C 2db
LTC6412 11 6412f 6db gain control step 70mhz time domain response 10db gain control step 70mhz time domain response 20db gain control step 70mhz time domain response typical performance characteristics electrical performance in test circuits a and b at t a = 25c and v cc = 3.3v unless otherwise noted. shdn step at g max with en = 0v 70mhz time domain response shdn step at g = 3db with en = 0v 70mhz time domain response overdrive compression at g max 70mhz time domain response overdrive recovery at g max 70mhz time domain response output en step at g max 140mhz time domain response shdn supply current time domain response time (ns) 0 voltage (v) 0.4 0.6 0.8 400 6412 g34 0.2 0 C0.6 C0.4 100 200 300 50 150 250 350 C0.2 1.2 1.0 external rf switch pulse small signal 15db compressed rf out into 50, 10db attenuated peak rf out = 14dbm time (ns) 0 voltage (v) 2.5 en 2.0 1.5 1.0 0.5 0 C0.5 C1.0 C1.5 160 6412 g35 40 80 120 200 140 20 60 100 180 rf out 50 peak rf out = 10dbm time (ms) 0 supply current (ma) shdn pin voltage (v) 4.0 6412 g36 80 40 100 60 120 20 0 2.0 0 3.0 1.0 1.0 0.5 2.0 1.5 3.0 3.5 4.5 2.5 5.0 012345 time (s) 6412 g29 voltage (v) rf out 50 peak rf out = 4dbm Cv g (0.5v/div) 020 20db 10db 0db peak gain compression 40 60 80 100 time (s) 6412 g33 voltage (v) rf out 50 peak rf out = 14dbm 0 100 200 300 400 500 time (s) 6412 g31 voltage (v) rf out 50 peak rf out = 4dbm shdn (1v/div) 0 100 200 300 400 500 time (s) 6412 g32 voltage (v) rf out 50 peak rf out = 4dbm shdn (1v/div) 012345 time (s) 6412 g28 voltage (v) rf out 50 peak rf out = 4dbm Cv g (0.25v/div) 012345 time (s) 6412 g30 voltage (v) rf out 50 peak rf out = 4dbm Cv g (0.5v/div)
LTC6412 12 6412f pin functions gnd (pins 1, 8, 12, 15, 18, 20, 23): ground. pins are connected to each other internally. for best rf performance, all ground pins should be connected to the printed circuit board ground plane. +in (pin 2): positive signal input pin. has an inter- nally generated dc bias. a 10nf dc blocking capacitor is recommended. Cin (pin 3): negative signal input pin. has an inter- nally generated dc bias. a 10nf dc blocking capacitor is recommended. v cm (pins 4, 5): input common mode voltage pins. two pins are tied together internally and serve as a virtual ground for the differential inputs, +in and Cin. capaci- tive decoupling to ground with 10nf close to the pins is recommended to help terminate any residual common mode input signal. v cc (pins 6, 13, 19, 24): positive power supply. all four pins must be tied to the same voltage, usually 3.3v. bypass each pin with 1000pf and 0.1f capacitors close to the pins. decl1 (pin 7): decoupling pin. serves to reduce internal noise. bypass to ground with a 0.1f capacitor close to the pin. +v g (pin 9): positive gain control pin. input signal pin used for positive mode gain control. otherwise, pin is typically connected to v ref for negative mode gain control. pin is internally pulled to ground with a 10k resistor. in positive gain slope mode, the gain control slope is approximately +32db/v at 140mhz with a gain control range of 0.1v to 1.1v. v ref (pin 10): internal bias voltage pin. typically tied to Cv g pin for positive gain control or tied to +v g for nega- tive gain control. determines the midpoint voltage of the gain-vs-v g characteristic. bypass to ground with 0.1f capacitor close to the pin. not intended for use as an external reference voltage. Cv g (pin 11): negative gain control pin. input signal pin used for negative mode gain control. otherwise, pin is typically connected to v ref for positive mode gain con- trol. pin is internally pulled to ground with a 10k resistor. in negative gain slope mode, the gain control slope is approximately C32db/v at 140mhz with a gain control range of 0.1v to 1.1v. decl2 (pin 14): decoupling pin. serves to reduce internal noise. bypass to ground with a 1000pf capacitor close to the pin. Cout (pin 16): negative ampli? er output pin. a trans- former with a center tap tied to v cc or a choke inductor is recommended to conduct dc quiescent current to the open-collector output device. for best performance, dc bias voltage to Cout must be within 100mv of v cc . +out (pin 17): positive ampli? er output pin. a trans- former with a center tap tied to v cc or a choke inductor is recommended to conduct dc quiescent current to the open-collector output device. for best performance, dc bias voltage to +out must be within 100mv of v cc . en (pin 21): output signal enable pin. pin is internally pulled high with 100k to v cc . assert pin to a low volt- age to enable the output ampli? er signal. output ampli? er impedance and dc current are not affected by the en state. connect pin to ground if enable function is not used. shdn (pin 22): shutdown pin. pin is internally pulled high with 100 k to v cc . assert pin to a low voltage to shut down the circuit and greatly reduce the supply current. proper sequencing of the en and shdn pins is required to avoid non-monotonic output signal behavior. see applications information section for details. connect pin to v cc if shutdown function is not used. exposed pad (pin 25): ground. the exposed pad should have multiple via holes to an underlying ground plane for low inductance and good thermal dissipation.
LTC6412 13 6412f block diagram dc test circuit 9 2 buffer/ output amplifier attenuator control reference and bias control +v g +in 3 Cin 4 5 v cm v cm 10 v ref 11 1 Cv g gnd 8 gnd 12 gnd 15 gnd 21 en 22 24 19 13 6 shdn 18 gnd 15 gnd v cc v cc v cc v cc 23 gnd decl2 6412 bd 25 14 decl1 7 Cout 16 +out 17 exposed pad reference and bias control ? ? ? ? ? ? ? ? ? gnd v cc v cm shdn en 0.1f 0.1f gain control (negative slope) 0.1f 100 6412 tc 100 Cout v supply v cc + 2.3v v supply v cc + 2.3v LTC6412 v cc 2.2v 0.8v +out Cin +in Cin +in Cout v out(diff) = (+out) C (Cout) v out(cm) = [(+out) + (Cout)]/2 v in(diff) = (+in) C (Cin) v in(cm) = [(+in) + (Cin)]/2 +out decl1 decl2 +v g Cv g v ref 0.1f 0.1f
LTC6412 14 6412f operation the LTC6412 employs an interpolated, tapped attenuator circuit architecture to generate the variable-gain charac- teristic of the ampli? er. the tapped attenuator is fed to a buffer and output ampli? er to complete the differential signal path shown in the block diagram. this circuit architecture provides good rf input power handling ca- pability along with a constant output noise and output ip3 characteristic that are desirable for most if signal chain applications. the internal control circuitry takes the gain control signal from the v g terminals and converts this to an appropriate set of control signals to the attenuator ladder. the attenuator control circuit ensures that the linear-in-db gain response is continuous and monotonic over the gain range for both slow and fast moving input control signals while exhibiting very little input impedance variation over gain. these design considerations result in a gain-vs-v g characteristic with a 0.1db ripple and a 0.5s gain response time that is slower than a similar digital step attenuator design. an often overlooked characteristic of an analog-controlled vga is upconverted amplitude modulation (am) noise from the gain control terminals. the vga behaves as a 2-quadrant multiplier, so some minimal care is required to avoid excessive am sideband noise generation. the table below demonstrates the effect of the baseline 20nv/ hz equivalent input control noise from the LTC6412 circuit along with the effect of a higher combined input noise due to a noisy external control circuit. control input total noise voltage (nv/ hz ) peak am noise at 10khz offset near maximum gain (dbc/hz) 20 C142 40 C136 70 C131 100 C128 200 C122 the baseline equivalent 20nv/ hz input noise is seen to produce worst-case am sidebands of C142dbc/hz which is near the C147dbm/hz output noise ? oor at maximum gain for a nominal 0dbm output signal. an input control noise voltage less than 80nv/ hz is generally recommended to avoid measurable am sideband noise. while op amp control circuit output noise voltage is usually below 80nv/ hz , some low power dac outputs exceed 150nv/ hz . dacs with output noise in the range of 100nv/ hz to 150nv/ hz can usually be accommodated with a suitable 2:1 or 3:1 resistor divider network on the dac output to suppress the noise amplitude by the same ratio. noisy dacs in excess of 150nv/ hz should be avoided if minimal am noise is important in the application.
LTC6412 15 6412f applications information introduction the LTC6412 is a high linearity, fully-differential analog- controlled variable-gain ampli? er (vga) optimized for ap- plication frequencies in the range of 1mhz to 500mhz. the vga architecture provides a constant oip3 and constant output noise level (nf + gain) over the 31db gain-control range and thus exhibits a uniform spurious-free dynamic range (sfdr) over gain. this constant sfdr characteristic is ideal for use in receiver if chains that are upstream from a signal sink such as a demodulator or adc. the low supply voltage requirements and fully differential design are compatible with many other ltc mixer, ampli? er and adc products for use in compact, low voltage, fully differential receiver chains. for non-differential systems, the 50 input impedance and 200 output impedance are easily converted to single-ended 50 ports with in- expensive 1:1 and 4:1 baluns. gain characteristics the LTC6412 provides a continuously adjustable gain range of C14db to 17db that is linear-in-db with respect to the control voltages applied to +v g and Cv g . these control pins can be operated with a differential signal, but it is more common to operate one of the v g pins with a single-ended control signal while connecting the other v g pin to the provided v ref pin. in this way, either a positive gain-control slope or negative gain-control slope is easily achieved: negative gain-control slope. tie +v g to v ref and apply gain control voltage to the Cv g pin. gain decreases with increasing Cv g voltage. positive gain-control slope. tie Cv g to v ref and apply gain control voltage to the +v g pin. gain increases with increasing +v g voltage. when connected in this typical single-ended con? guration, the active control input range extends from 0.1v to 1.1v. this control input range can be extended using a resistor divider with a suitably low output resistance. for example, two series resistors of 1k each would extend the control input range from 0.2v to 2.2v while providing an effective 500 thevinin equivalent source resistance, a relatively small loading effect compared to the 10k input resistance of the +v g /Cv g terminals. port characteristics the LTC6412 provides a nominal 50 differential input impedance and 200 differential output impedance over the operating frequency range. the input impedance characteristic derives from the dif- ferential attenuator ladder shown in the block diagram. the internal circuit controls the rf connections to this attenuator ladder and generates the appropriate common mode dc voltage to this port. the differential attenuator ladder creates a virtual ground node that needs a capacitor bypass to ground at the v cm pin to effectively attenuate any common mode signal presented to the input port. the +v in and Cv in pins are connected to the input signal through dc blocking capacitors as shown in test circuit a and test circuit b, figures 1-4. the output impedance characteristic derives from the open-collector equivalent circuit shown in figure 7. the action of the differential shunt, lowpass ? lter, and internal feedback presents an effective differential output imped- ance of 200 to 300 between the +out and Cout pins over the operating band. the +v out and Cv out pins are connected to the output port using shunt inductors or a transformer to provide a dc path to the supply voltage. the dc block to the circuit output is usually accomplished using series capacitors. these blocking capacitors can be avoided if a ? ux transformer is used at the output. figure 9 illustrates a few common inductor and balun transformer methods for coupling the ac signal and dc supply to the output pins. this is discussed further in the typical ap- plication circuits section. power supplies inductance to the supply path can degrade the performance of the LTC6412. it is recommended that low inductance bypass capacitors are installed very close to each of the v cc pins. 1000pf and 0.1f parallel capacitors are recom- mended with the smaller capacitor placed closer to the v cc pin. do not leave any supply pins disconnected. for best performance, dc bias voltage to the +out and Cout pins
LTC6412 16 6412f applications information must be within 100mv of v cc . the exposed pad on the underside of the package must be connected to ground with low inductance and low thermal resistance. refer to details of dc1464a (test circuit a) for an example of proper grounding and supply decoupling. failure to provide low impedance supply and ground at high frequencies can cause oscillations and increased distortion. enable/shutdown both the en pin and shdn pin are self-biased to v cc through their respective 100k pull-up resistors, so the default open-pin state is powered on with the output ampli- ? er signal path disabled. pulling the en pin low completes the signal path from the attenuator ladder through the output ampli? er. the en pin essentially provides a fast muting function while the shdn pin provides slower power on/off function. for applications requiring the shdn function, it is recom- mended that the output ampli? er signal path be disabled with a high en voltage before transitioning the shdn signal. when enabling the ampli? er, allow at least 5ms dwell time between the rising shdn transition and the falling en transition to avoid non-monotonic output signal behavior though the vga. the opposite delay sequence is recommended for the falling shdn transition, but this is less critical as the output signal amplitude will drop abruptly regardless of the en pin. shdn en t dwell t dwell 6412 ai01 layout/grounding the high frequency performance of the LTC6412 requires special attention to proper rf grounding, bias decoupling and termination. the recommended pcb stack-up for a 4-layer board is shown below for 1oz copper clad fr-4 laminate with a relative dielectric constant, r = 4.2-4.5 at 1ghz. metal 1 metal 2 metal 3 metal 4 rf signal fr4 12-18 mils fr4 20-30 mils fr4 not critical ground plane power plane gnd and lf signal 6412 ai02 the topside metal and silkscreen drawings for test circuit a illustrate the recommended decoupling capacitor place- ment, signal routing and grounding. ground vias directly beneath the exposed pad are critical; use as many as possible. ground vias to the other ground pins are less critical. esd the LTC6412 is protected with reverse-biased esd diodes on all i/o pins. if any i/o pin is forced one diode drop above the positive supply or one diode drop below the negative supply, then large currents may ? ow through the diodes. no damage to the devices will occur if the current is kept below 10 ma. the +out/Cout pins have additional series diodes to the positive supply and can sustain approximately 2v overshoot above the positive supply before conducting appreciable currents.
LTC6412 17 6412f signal compression characteristics the graph entitled, input and output p1db, illustrates an important characteristic of the LTC6412 vga. at gain settings above C5db, the output ampli? er limits the linear power handling capability, but at gain settings below C5db, the input attenuator ladder limits the linear power handling capability. the linear input power limitations at minimum gain do not affect the overall performance of a signal chain if the preceding mixer or ampli? er stage exhibits an op1db < 19dbm and an oip3 < 50dbm. test circuits the fully-differential nature of the LTC6412 design requires two test circuits to generate the performance information presented in this data sheet. test circuit a is dc1464a, a 2-port demonstration circuit with input/output balun transformers to allow for direct connection to a 2-port network analyzer or other single- ended 50 test system. the balun transformers limit the high and low frequency performance of the LTC6412 but allow for simple and reasonably accurate measurements from 70mhz to 380mhz. the gain control signal is supplied to either of the v g turrets for dc control measurements or through the v gain sma connector for transient control signal measurements. clip leads to the gain control turrets are susceptible to noise pickup and should be lowpass ? ltered to avoid am upconversion artifacts. while using the v g turrets, a 4.7f capacitor from the v gain sma input to ground provides an effective lowpass ? lter. typical data curves quoted for test circuit a are measured at the plane of the sma connectors and are not corrected for any losses introduced by the input and output baluns, estimated at approximately 0.5db and 1.2db, respectively. all typical ac data reported in this data sheet correspond to test circuit a, except for mixed-mode s-parameters of the form sdd21, scc21, etc. applications information test circuit b uses a 4-port network analyzer to measure differential mode and common mode s-parameters beyond the frequency limitations imposed by the balun transformers and associated circuitry. a matching calibra- tion set establishes the measurement reference planes shown in test circuit b. the output plane is de? ned at the edge of the package while the input plane is de? ned at the edge of the input pair of 0402 capacitors. the ic land and ground via pattern are identical to that shown for test circuit a. the ground via pattern directly beneath the package is critical to provide the proper rf ground to produce the rf characteristics quoted in this data sheet. all mixed-mode s-parameter typical data curves of the form sxyab correspond to test circuit b following the de? nitions described in figures 5 and 6. typical application circuits grounding and supply decoupling should closely follow the suggested layout shown for test circuit a, but the input and output networks can be customized to suit various application requirements. on the input side, the differential port impedance is very close to 50 over all gain settings and application frequen- cies. in a differential signal chain, the differential input signal is easily supplied from a preceding differential output stage with a suitable dc blocking capacitor of approximately 10nf. if the system employs a single-ended input signal to the vga, then a suitable balun is required to convert to a differential input signal. the passive conversion from 50 single-ended to 50 differential is most effectively accomplished with a 1:1 transmission-line balun such as the etc1-1-13 or maba-007159. these 1:1 balun devices are relatively inexpensive and offer excellent electrical characteristics such as low loss, broad band response and good phase matching.
LTC6412 18 6412f applications information on the output side, the differential port admittance is very close to 300||1.5pf across all gain settings and applica- tion frequencies. this output port circuit must provide a path for dc output supply current as well as any balun, matching, or ? ltering functions required by the application. thus, the design options for the output circuitry are more varied. a brief list of the more common output circuits is shown in figure 9 along with a few design guidelines to estimate component values. final design simulations should use the small-signal equivalent circuit model in figure 8 to properly account for loading effects of the output terminals. figure 9a shows the simplest differential output con? gura- tion employing two suitable inductors, l1 = l2, to pass the dc supply current without loading the output nodes at the application frequency. the pcb trace widths from the output pins should be narrow in keeping with the high impedance of these terminals; 8 to 10mil trace width on 1oz copper is a good choice. the 0.1f capacitors serve to dc block and decouple as needed. these capacitor values are adequate down to a few mhz and can be scaled down for higher application frequencies. if bandpass ? ltering is needed at the vga output of figure 9a, then l1 and l2 can be designed to resonate with a shunt capacitor, c o , at the frequency of interest, =1/c o (l1 + l2). alternately, l1 = l2 can be designed to resonate with two separate capacitors, c1 = c2, so any common mode noise is ? ltered as well. figure 9b shows a further variation of the tuned differential output where the dc blocking capacitors are brought inside the tank resonator to participate in the bandpass ? lter and transform the vga output impedance to a lower value. here too, the c o capacitor can be split into two separate shunt capacitors to ground, so any common mode noise is ? ltered as well. 6412 f01 6412 f02 figure 1. top silkscreen for dc1464a. test circuit a figure 2. top metal for dc1464a. test circuit a
LTC6412 19 6412f figure 3. demo board dc1464a circuit schematic. test circuit a applications information v cc gnd shdn LTC6412 en gnd v cc decl1 gnd +in Cin v cm v cm v cc v cc v cc v cc gnd 1 2 c5 10nf v cc v cc v cc c2 1000pf c3 0.1f c2 1000pf c4 0.1f c8 10nf c13 1000pf c14 0.1f c16 1000pf c22 0.1f c15 0.1f c11 10nf c17 0.1f ca1 1f cb1 4.7f note: [1] do not place c12 1000pf c21 0.1f +out Cout c6 0.1f c9 [1] c20 [1] c7 0.1f v cc r17 100 t1 1:1 3 1 2 3 5 r7 [1] r9 0 4 0db +in Cin 4 5 6 18 24 23 22 21 20 19 789101112 17 16 15 14 13 +out Cout gnd decl2 v cc gnd +v g v ref Cv g gnd ? ? v cc gnd 3.00v to 3.60v t3 1:1 t4 1:1 13 2 1 4 5 c18 0.1f c19 0.1f 2 3 5 r21 0 4 test in test out 6412 f03 ? ? ? ? r15 0 t2 4:1 1 2 3 5 4 r14 [1] v gain +v g Cv g r18 [1] r20 100 r19 0 ? r5 1k r6 1k r3 [1] r1 1k r4 1k r2 [1] v cc shdn en r22 0 balun t1, t3, t4 t2 part number tyco maba-007159 mini-circuits tcm4-19+ figure 9c shows a ? ux transformer used to achieve a 50 single-ended output. the ? ux transformer does not provide the large bandwidth typical of the output transmission-line transformer shown in figure 3, but it usually performs well over smaller bandwidths, especially when tuned with shunt capacitors (not shown). the ? ux transformer design eliminates dc blocking capacitors and is attrac- tive in rugged applications where the ampli? er output is subjected to esd events and other forms of transient electrical overstress that do not pass through a typical rf ? ux transformer such as the mabaes0061. figure 9d shows a discrete lc balun suitable for bandwidths of approximately 15% to 30%. larger bandwidths are dif? cult to achieve with the number of components shown, and smaller bandwidths are often limited by component tolerance effects. despite these limitations, the discrete lc balun can be a cost effective output circuit solution. at resonance, the tuned circuit produces an impedance transformation along with the differential-to-single-ended conversion. dc coupled operation the LTC6412 is intended for ac-coupled operation. the translation between the ? xed input dc common mode voltage and higher open-collector output dc bias point makes it impractical to use in dc-coupled applications.
LTC6412 20 6412f figure 4. 4-port analysis schematic. test circuit b v cc shdn en gnd v cm v ref decl1 decl2 +v g Cv g +in 10nf 10nf 10nf 3.3v 1nf 0.1f +out i dc Cout 6412 f04 0.1f 0.1f 0.1f gain control (C slope mode) input ref plane output ref plane LTC6412 Cin port 3 50 port 4 50 1/2 agilent e5071c port 1 50 port 2 50 1/2 agilent e5071c i dc 200 50 12.5 50 dut 1:1 ideal transformer with center tap 1:1 ideal transformer with center tap differential mode port 2 differential mode port 1 common mode port 2 common mode port 1 +out +in Cout Cin 6412 f05 figure 5. schematic of mixed-mode s-parameters reported for test circuit b figure 6. de? nition of mixed-mode s-parameters reported for test circuit b s xyab s xyab = stimulus port number response port number stimulus port mode response port mode d: differential mode (balanced) c: common mode (balanced) x mode signal output on port a y mode signal input on port b mode 6412 f06 applications information
LTC6412 21 6412f figure 7. large-signal output equivalent circuit schematic figure 8. small-signal output equivalent circuit model to buffer amp 150 0.3pf 0.3pf 8pf 5 5 5 5 +out Cout 6412 f06 lowpass filter 150 g m 300 differential mode admittance ideal 1:1 transformer with center tap common mode admittance 175 190 +out Cout z out 1.5pf 5pf 4pf 6412 f08 1nh 1nh applications information
LTC6412 22 6412f applications information v cc 0.1f 0.1f c1 10mil line width l1 l2 (a) c2 0.1f c o z out = 200 differential l1 = l2 c1 = c2 note: dashed line components are for bandpass filtering (see text) l1 = l2 c1 = c2 t2 = mabaes0061 z out = 50 single ended +out Cout LTC6412 v cc 0.1f l1 l2 (b) c2 t2 4:1 c1 c o +out Cout LTC6412 v cc 0.1f 0.1f c1 c2 lc balun 6412 f09 l1 l choke l2 (d) +out Cout LTC6412 v cc 0.1f (c) +out Cout LTC6412 at resonance, l1 = l2 = l c1 = c2 = c differential z out = 200 2 + + 1 c o 1 c2 1 c1 1 c o f o = x c = at resonance, single ended 1 2 lc 1 2f o c z out = x c 2 200 figure 9. output ac/dc coupling, filter and balun circuit design options
LTC6412 23 6412f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) 4.00 p 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 24 23 1 2 bottom viewexposed pad 2.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 p 0.05 0.25 p 0.05 0.50 bsc 2.45 p 0.05 (4 sides) 3.10 p 0.05 4.50 p 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 s 45 o chamfer
LTC6412 24 6412f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0509 ? printed in usa related parts part number description comments fixed gain if ampli? ers/adc drivers lt1993-2, lt1993-4, lt1993-10 800mhz differential ampli? er/adc drivers C72dbc im3 at 70mhz 2v p-p composite, a v = 2v/v, 4v/v, 10v/v ltc6400-8, ltc6400-14, ltc6400-20, ltc6400-26 1.8ghz low noise, low distortion differential adc drivers C71dbc im3 at 240mhz 2v p-p composite, i s = 90ma, a v = 8db, 14db, 20db, 26db ltc6401-8, ltc6401-14, ltc6401-20, ltc6401-26 1.3ghz low noise, low distortion differential adc drivers C74dbc im3 at 140mhz 2v p-p composite, i s = 50ma, a v = 8db, 14db, 20db, 26db lt6402-6, lt6402-12, lt6402-20 300mhz differential ampli? er/adc drivers C71dbc im3 at 20mhz 2v p-p composite, a v = 6db, 12db, 20db ltc6410-6 1.4ghz differential if ampli? er with con? gurable input impedance oip3 = 36dbm at 70mhz, flexible interface to mixer if port ltc6416 2ghz, 16-bit differential adc buffer C72dbc im2 at 300mhz 2v p-p composite, i s = 42ma, e n = 2.8nv/ hz , a v = 0db, 300mhz 0.1db bandwidth ltc6420-20 dual 1.8ghz low noise, low distortion differential adc drivers dual version of the ltc6400-20, a v = 20db ltc6421-20 dual 1.3ghz low noise, low distortion differential adc drivers dual version of the ltc6401-20, a v = 20db if ampli? ers/adc drivers with digitally controlled gain lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain oip3 = 47dbm at 100mhz, gain range 10.5db to 33db by 1.5db lt5524 low distortion if ampli? er/adc driver with digitally controlled gain oip3 = 40dbm at 100mhz, gain range 4.5db to 37db by 1.5db lt5554 high dynamic range 7-bit digitally controlled if vga/adc driver oip3 = 46dbm at 200mhz, gain range 1.725 to 17.6db by 0.125db baseband differential ampli? ers lt1994 low noise, low distortion differential ampli? er/adc driver 16-bit snr, sfdr at 1mhz, rail-to-rail outputs ltc6403-1 low noise rail-to-rail output differential ampli? er/adc driver 16-bit snr, sfdr at 3mhz, rail-to-rail outputs, e n = 2.8nv/ hz ltc6404-1, ltc6404-2 low noise rail-to-rail output differential ampli? er/adc driver 16-bit snr, sfdr at 10mhz, rail-to-rail outputs, e n = 1.5nv/ hz , ltc6404-1 is unity-gain stable, ltc6404-2 is gain-of-2 stable ltc6406 3ghz rail-to-rail input differential ampli? er/adc driver C65dbc im3 at 50mhz 2v p-p composite, rail-to-rail inputs, e n = 1.6nv/ hz , 18ma lt6411 low power differential adc driver/dual selectable gain ampli? er C83dbc im3 at 70mhz 2v p-p composite, a v = 1, C1 or 2, 16ma, excellent for single-ended to differential conversion low noise dac for gain control ltc2630-10 low power, internal reference, single supply 10-bit dac spi input, 2.5v output range, resistor divide output by ~2:1 ltc2640-10 low power, internal reference, single supply 10-bit dac spi input, 2.5v output range, resistor divide output by ~2:1 ltc2641-12 low noise, low power, single supply 12-bit dac spi input, low glitch impulse, power-on to zero scale ltc2642-12 low noise, low power, single supply 12-bit dac spi input, low glitch impulse, power-on to midscale

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